Wireless communication devices, such as mobile phone handsets, require a very high level of integration of hardware and firmware/software in order to achieve the necessary density of functionality, i.e. to realise the necessary functionality in a minimum device volume and at a minimum cost. An optimal wireless communication device design must also minimise power consumption in order to increase the battery call time and/or stand-by time.
Wireless communication devices also incorporate a number of distinct and operably coupled sub-systems, in order to provide the wide variety of functions and operations that a complex wireless communication device needs to perform. Such sub-systems comprise radio frequency power amplification functions, radio frequency integrated circuits (RFIC) comprising radio frequency generation, amplification, filtering, etc. functions, baseband integrated circuits (BBIC) comprising audio circuits, encoding/decoding, (de)modulation functions, as well as processing functions, etc and memory units.
Interfaces, which are often standardised to allow commonality and increased functionality between different chip-set manufacturers and different handset manufacturers, are often standardised for communicating between the respective sub-systems.
One typical interface found in a wireless communication device is the interface between a baseband integrated circuit (BBIC) and a radio frequency integrated circuit—(RFIC). Contact pins on ICs are used to route electrical signals between devices/elements/functions. It is generally desirable to minimise the number of pins in ICs used in wireless communication devices, as the use of extra pins, for example on a BBIC-RFIC interface, increase IC area, increase IC cost and complexity and increase power consumption.
In the field of mobile phones, a consortium of mobile phone manufacturers has been formed to define various sub-system interfaces, particularly interfaces between variants of second generation cellular phones (2.xG) when migrating to cover additional, future wireless communication technologies, such as multimode transceivers additionally employing third generation (3G) wideband code division multiple access (WCDMA) technology. This consortium is known as ‘DigRF’, and details of the defined interfaces and functionality thereof, particularly in multimode mobile phone scenario, can be found on their web site at www.digrf.com. Multimode operational specs are not yet available.
One interface being standardised by the DigRF consortium is the BB-RF interface, which encompasses a serial data/control interface for Receive (Rx) and Transmit (Tx) variants of second generation of cellular phone (2.xG) chipsets. When defining the interface to also accommodate the increased complexity and data rate required for 3G technologies, it is clearly advantageous to minimise the IC pin count.
The 2.xG standard contains a strobe signal for conveying layer 1 timing information, for example between the RFIC and BBIC. Notably, the strobe signal's width and magnitude are fixed. Thus, all strobes are indistinguishable from each other. Furthermore, the interface standard was developed with a 2.xG transceiver (TRX) only in mind. On the BBIC RFIC interface the Strobe signal is provided to support precise timing of events inside the RFIC
However, it is envisaged that wireless communication devices in the future may need to accommodate multiple communication modes. So far, no solution has been proposed to convey layer 1 timing information to multiple transceivers using the same interface. The inventors of the present invention have recognised and appreciated that the obvious solution of duplicating pins, such as a 2.xG IC pin supporting strobe signals, to accommodate multiple modes is wasteful of valuable resources.
IBM's U.S. Patent Application—US 200430071015 A1—discloses a use of strobe signals in the field of SDRAM (memory) interfaces. A ‘single’ strobe signal is selected to accurately latch data to a Synchronous Dynamic Random Access Memory (SDRAM). A concept of transmitting a single strobe signal from different sources is also described.
However, the technique proposed in US 200430071015 A1 would still not solve the aforementioned problem of wasting valuable resources, as it suggests latching a single strobe signal, per function.
An U.S. Patent—U.S. Pat. No. 6,715,096 B2—inventor of Kuge et al. and applicant of Renesas Technology Corporation, describes a further technique of using strobe signals with interfaces to memory ICs. U.S. Pat. No. 6,715,096 B2 discloses an interface circuit device for performing data sampling at optimum strobe timing, by using stored data window information to determine the strobe timing. U.S. Pat. No. 6,715,096 B2 highlights an interface where data is latched correctly into memory by selecting an optimum delay on a latch strobe for a write/read (WR) memory.
Thus, a need exists for a mechanism, for example within a wireless communications device, to incorporate integrated circuits/sub-systems and a corresponding control interface that support strobe signals to multiple devices (for example transceivers), without incurring increased cost or complexity or increased pin count.